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H
Hermetically Sealed, Low IF, Wide VCC, Logic Gate Optocouplers Technical Data
HCPL-520X* 5962-88768 HCPL-523X HCPL-623X HCPL-625X 5962-88769
*See matrix for available extensions.
Features
* Dual Marked with Device Part Number and DESC Drawing Number * Manufactured and Tested on a MIL-PRF-38534 Certified Line * QML-38534, Class H and K * Four Hermetically Sealed Package Configurations * Performance Guaranteed over -55C to +125C * Wide VCC Range (4.5 to 20 V) * 350 ns Maximum Propagation Delay * CMR: > 10,000 V/s Typical * 1500 Vdc Withstand Test Voltage * Three State Output Available * High Radiation Immunity * HCPL-2200/31 Function Compatibility * Reliability Data * Compatible with LSTTL, TTL, and CMOS Logic
* Isolated Bus Driver (Single Channel) * Pulse Transformer Replacement * Ground Loop Elimination * Harsh Industrial Environments * Computer-Peripheral Interfaces
eliminates the potential for output signal chatter. The detector in the single channel units has a tri-state output stage
Truth Tables
(Positive Logic) Multichannel Devices Input Output On (H) H Off (L) L
Description
These units are single, dual and quad channel, hermetically sealed optocouplers. The products are capable of operation and storage over the full military temperature range and can be purchased as either standard product or with full MIL-PRF-38534 Class Level H or K testing or from the appropriate DESC Drawing. All devices are manufactured and tested on a MIL-PRF-38534 certified line and are included in the DESC Qualified Manufacturers List QML-38534 for Hybrid Microcircuits. Each channel contains an AlGaAs light emitting diode which is optically coupled to an integrated high gain photon detector. The detector has a threshold with hysteresis which provides differential mode noise immunity and
Single Channel DIP Input Enable On (H) H Off (L) H On (H) L Off (L) L
Output Z Z H L
Functional Diagram
Multiple Channel Devices Available
VCC VO
Applications
* Military and Space * High Reliability Systems * Transportation and Life Critical Systems * High Speed Line Receiver
VE GND
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. 1-512 5965-3005E
which allows for direct connection to data buses. The output is noninverting. The detector IC has an internal shield that provides a guaranteed common mode transient immunity of up to 10,000 V/s. Improved power supply rejection eliminates the need for special power supply bypass precautions. Package styles for these parts are 8 pin DIP through hole (case outline P), 16 pin DIP flat pack (case outline F), and leadless
ceramic chip carrier (case outline 2). Devices may be purchased with a variety of lead bend and plating options, see Selection Guide Table for details. Standard Military drawing (SMD) parts are available for each package and lead style. Because the same electrical die (emitters and detectors) are used for each channel of each device listed in this data sheet, absolute maximum ratings, recommended operating conditions, electrical
specifications, and performance characteristics shown in the figures are identical for all parts. Occasional exceptions exist due to package variations and limitations and are as noted. Additionally, the same package assembly processes and materials are used in all devices. These similarities give justification for the use of data obtained from one part to represent other part's performance for die related reliability and certain limited radiation test results.
Selection Guide-Package Styles and Lead Configuration Options
Package Lead Style Channels Common Channel Wiring HP Part # & Options Commercial MIL-PRF-38534, Class H MIL-PRF-38534, Class K Standard Lead Finish Solder Dipped Butt Cut/Gold Plate Gull Wing/Soldered SMD Part # Prescript for all below Either Gold or Solder Gold Plate Solder Dipped Butt Cut/Gold Plate Butt Cut/Soldered Gull Wing/Soldered 8 Pin DIP Through Hole 1 None 8 Pin DIP Through Hole 2 VCC, GND 16 Pin Flat Pack Unformed Leads 4 VCC, GND 20 Pad LCCC Surface Mount 2 None
HCPL-5200 HCPL-5201 HCPL-520K Gold Plate Option #200 Option #100 Option #300 59628876801PX 8876801PC 8876801PA 8876801YC 8876801YA 8876801XA
HCPL-5230 HCPL-5231 HCPL-523K Gold Plate Option #200 Option #100 Option #300 59628876901PX 8876901PC 8876901PA 8876901YC 8876901YA 8876901XA
HCPL-6250 HCPL-6251 HCPL-625K Gold Plate
HCPL-6230 HCPL-6231 HCPL-623K Soldered Pads
59628876903FX 8876903FC
596288769022X 88769022A
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Functional Diagrams
8 Pin DIP Through Hole 1 Channel 8 Pin DIP Through Hole 2 Channels 16 Pin Flat Pack Unformed Leads 4 Channels
1 16 VCC 15
20 Pad LCCC Surface Mount 2 Channels
15 VCC2 19 VO2 GND2 VO1 GND1 7 8 VCC1 13 12
1 2 3 4
VCC VO
8 7 6 5
1 2 3 4
VCC VO1
8 7
2 3 4
VO1 14 VO2 13 VO3 12 VO4 11 GND 10 9
20
VO2
VE GND
6 5
5 6 7 8
2 3
10
GND
Note: Multichannel DIP and flat pack devices have common VCC and ground. Single channel DIP has an enable pin 6. LCCC (leadless ceramic chip carrier) package has isolated channels with separate VCC and ground connections.
Outline Drawings
16 Pin Flat Pack, 4 Channels
7.24 (0.285) 6.99 (0.275)
2.29 (0.090) MAX.
1.27 (0.050) REF. 11.13 (0.438) 10.72 (0.422)
0.46 (0.018) 0.36 (0.014) 8.13 (0.320) MAX.
2.85 (0.112) MAX.
0.88 (0.0345) MIN. 0.89 (0.035) 0.69 (0.027) 5.23 (0.206) MAX. 9.02 (0.355) 8.76 (0.345)
0.31 (0.012) 0.23 (0.009)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
20 Terminal LCCC Surface Mount, 2 Channels
8.70 (0.342) 9.10 (0.358) 4.95 (0.195) 5.21 (0.205) 1.78 (0.070) 2.03 (0.080) 1.02 (0.040) (3 PLCS) 1.14 (0.045) 1.40 (0.055) 8.70 (0.342) 9.10 (0.358) 4.95 (0.195) 5.21 (0.205) 1.78 (0.070) 2.03 (0.080) 0.64 (0.025) (20 PLCS) 1.52 (0.060) 2.03 (0.080)
8 Pin DIP Through Hole, 1 and 2 Channel
9.40 (0.370) 9.91 (0.390) 0.76 (0.030) 1.27 (0.050) 4.32 (0.170) MAX. 8.13 (0.320) MAX. 7.16 (0.282) 7.57 (0.298)
TERMINAL 1 IDENTIFIER 2.16 (0.085) METALIZED CASTILLATIONS (20 PLCS) 0.51 (0.020)
0.51 (0.020) MIN.
3.81 (0.150) MIN.
0.20 (0.008) 0.33 (0.013)
2.29 (0.090) 2.79 (0.110)
0.51 (0.020) MAX. NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
7.36 (0.290) 7.87 (0.310)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES). SOLDER THICKNESS 0.127 (0.005) MAX.
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Leaded Device Marking
HP LOGO HP P/N DESC SMD* DESC SMD* PIN ONE/ ESD IDENT HP QYYWWZ XXXXXX XXXXXXX XXX USA * 50434 COMPLIANCE INDICATOR,* DATE CODE, SUFFIX (IF NEEDED) COUNTRY OF MFR. HP FSCN*
Leadless Device Marking
HP LOGO HP P/N PIN ONE/ ESD IDENT COUNTRY OF MFR. HP QYYWWZ XXXXXX * XXXX XXXXXX USA 50434 COMPLIANCE INDICATOR,* DATE CODE, SUFFIX (IF NEEDED) DESC SMD* DESC SMD* HP FSCN*
*QUALIFIED PARTS ONLY
*QUALIFIED PARTS ONLY
Hermetic Optocoupler Options
Option 100 Description Surface mountable hermetic optocoupler with leads trimmed for butt joint assembly. This option is available on commercial and hi-rel product in 8 pin DIP (see drawings below for details).
4.32 (0.170) MAX.
0.51 (0.020) MIN. 2.29 (0.090) 2.79 (0.110)
1.14 (0.045) 1.40 (0.055) 0.51 (0.020) MAX. NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
0.20 (0.008) 0.33 (0.013) 7.36 (0.290) 7.87 (0.310)
200
300
Lead finish is solder dipped rather than gold plated. This option is available on commercial and hi-rel product in 8 pin DIP. DESC Drawing part numbers contain provisions for lead finish. All leadless chip carrier devices are delivered with solder dipped terminals as a standard feature. Surface mountable hermetic optocoupler with leads cut and bent for gull wing assembly. This option is available on commercial and hi-rel product in 8 pin DIP (see drawings below for details). This option has solder dipped leads.
5.57 (0.180) MAX. 0.20 (0.008) 0.33 (0.013) 9.65 (0.380) 9.91 (0.390)
5.57 (0.180) MAX.
0.51 (0.020) MIN. 2.29 (0.090) 2.79 (0.110)
1.40 (0.055) 1.65 (0.065) 0.51 (0.020) MAX.
5 MAX.
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
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Absolute Maximum Ratings
Storage Temperature Range, TS .................................. -65C to +150C Operating Temperature, TA ......................................... -55C to +125C Case Temperature, TC ................................................................ +170C Junction Temperature, TJ ................................................................................... +175C Lead Solder Temperature .............................................. 260C for 10 s Average Forward Curre, IF AVG (each channel) ............................. 8 mA Peak Input Current, IF PK (each channel) ............................... 20 mA[1] Reverse Input Voltage, VR (each channel) ....................................... 3 V Supply Voltage ,VCC .............................................. 0.0 V min., 20 V max. Average Output Current, IO (each channel) ................................. 15 mA Output Voltage, VO (each channel) .................... -0.3 V min., 20 V max. Package Power Dissipation, Pd (each channel) ......................... 200 mW Single Channel Product Only Tri-State Enable Voltage, VE ............................... -0.3 V min., 20 V max.
8 Pin Ceramic DIP Single Channel Schematic
ANODE
CATHODE
Note enable pin 6. An external 0.01 F to 0.1 F bypass capacitor is recommended between VCC and ground for each package type.
ESD Classification
(MIL-STD-883, Method 3015) HCPL-5200/01, HCPL-6230/31 ........................................... (), Class 1 HCPL-5230/31, HCPL-6250/51 ....................................... (Dot), Class 3
Recommended Operating Conditions
Parameter Power Supply Voltage Input Current, High Level, Each Channel Input Voltage, Low Level, Each Channel Fan Out (TTL Load) Each Channel Symbol VCC IFH VFL N Min. 4.5 2 0 Max. 20 8 0.8 4 Units V mA V
Single Channel Product Only High Level Enable Voltage VEH Low Level Enable Voltage VEL
2.0 0
20 0.8
V V
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Electrical Characteristics
TA = -55C to +125C, 4.5 V VCC 20 V, 2 mA IF(ON) 8 mA, 0 V VF(OFF) 0.8 V, unless otherwise specified.
Parameter Logic Low Output Voltage Logic High Output Voltage Output Leakage Current (VOUT > VCC) Logic Low Supply Current Single Channel ICCL Dual Channel Quad Channel Single Channel Logic High Supply Current Dual Channel Quad Channel Logic Low Short Circuit Output Current Logic High Short Circuit Output Current Input Forward Voltage Input Reverse Breakdown Voltage Input-Output Insulation Leakage Current ICCH VCC = 5.5 V VCC = 20 V
CC
Sym. VOL VOH IOHH
Test Conditions IOL = 6.4 mA (4 TTL Loads) IOH = -2.6 mA (**VOH = VCC - 2.1 V) IOH = -0.32 mA VO = 5.5 V VO = 20 V
CC
Group A[11] Limit Subgroups Min. Typ.* Max. Units Fig. Notes 1, 2, 3 1, 2, 3 NA 1, 2, 3 4.5 1, 2, 3 5.3 9.0 2.4 ** 3.1 100 500 6 7.5 12 15 24 30 4.5 6 9 12 18 24 mA 2, 3 35 -10 1, 2, 3 1, 2, 3 1, 2, 3 1 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 1000 10,000 1000 10,000 173 118 350 350 1.0 3 1.0 1.3 -25 1.8 V V A V/s V/s ns ns 9 9 5, 6 5, 6 4 mA 2, 3 2 2 4, 5 2, 6, 12 2, 6, 12 2, 7 2, 7 mA mA A 2 0.5 V V 2, 3 2 1, 3 2
IF = 8 mA VCC = 4.5 V
VCC = 5.5 V VF = 0 V V = 20 V VE = Don't Care VCC = 5.5 V VF1 = VF2 = 0 V VCC = 20 V VCC = 5.5 V VF1 = VF2 = VF3 = VF4 = 0 V VCC = 20 V VCC = 5.5 V IF = 8 mA VE = Don't Care VCC = 20 V
10.6 14 17 2.9 1, 2, 3 3.3 5.8 IF1 = IF2 = 8 mA
F3 F3
6.6 9 11 20
VCC = 5.5 V IF1 = IF2 = V= V = 20 V I F3= VF4 = 8 mA V= IF4 = 8 mA VO = VCC = 5.5 V IOSL VO = VCC = 20 V VCC = 5.5 V IOSH VF BVR II-O VCC = 20 V IF = 8 mA IR = 10 A VI-O = 1500 Vdc, t = 5s RH = 45%, TA = 25C IF = 8 mA VO = GND VF = 0 V 1, 2, 3
Logic High Common Mode |CMH| IF = 2 mA, VCM = 50 VP-P Transient Immunity Logic Low Common Mode |CML| IF = 0 mA, VCM = 50 VP-P Transient Immunity Propagation Delay Time to Logic Low Propagation Delay Time to Logic High tPHL tPLH
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TA = -55C to +125C, 4.5 V VCC 20 V, 2 mA IF (ON) 8 mA, 0 V VF(OFF) 0.8 V, 2.0 V VEH 20 V, 0 V VEL 0.8 V, unless otherwise specified.
Parameter High Impedance State Output Current Sym. IOZL Test Conditions VO = 0.4 V VO = 2.4 V IOZH Logic High Enable Voltage Logic Low Enable Voltage Logic High Enable Current VEH VEL VEN = 2.7 V IEH VEN = 5.5 V VEN = 20 V Logic Low Enable Current IEL VEN = 0.4 V 1, 2, 3 1, 2, 3 0.004 VO = 5.5 V VO = 20 V 1, 2, 3 1, 2, 3 2.0 0.8 20 100 250 -0.32 mA VEN = 2 V, VF = 0 V VEN = 2 V, IF = 8 mA Group A[11] Subgroups 1, 2, 3 Limits Min. Typ.* Max. Units -20 20 1, 2, 3 100 500 V V A A A Fig. Notes
Electrical Characteristics Single Channel Product Only
*All typical values are at VCC = 5 V, TA = 25C, IF(ON) = 5 mA unless otherwise specified.
Typical Characteristics
All typical values are at TA = 25C, VCC = 5 V, IF(ON) = 5 mA unless otherwise specified. Parameter Input Current Hysteresis Input Diode Temperature Coefficient Resistance (Input-Output) Capacitance (Input-Output) Input Capacitance Output Rise Time (10-90%) Output Fall Time (90-10%) Symbol Typ. IHYS 0.07 VF ---- -1.25 TA RI-O 1013 CI-O 2.0 CIN 20 tr 45 tf 10 Units mA mV/C pF pF ns ns Test Conditions VCC = 5 V IF = 8 mA VI-O = 500 Vdc f = 1 MHz VF = 0 V, f = 1 MHz 5, 7 5, 7 Fig. 3 Notes 2 2 2, 8 2, 8 2, 10 2 2
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Typical Characteristics (cont'd.)
All typical values are at TA = 25C, VCC = 5 V, IF(ON) = 5 mA, unless otherwise specified. Single Channel Product Only Parameter
Output Enable Time to Logic High Output Enable Time to Logic Low Output Disable Time from Logic High Output Disable Time from Logic Low
Symbol
tPZH tPZL tPHZ tPLZ
Typ.
30 30 45 55
Units
ns ns ns ns
Test Conditions
Fig.
8 8 8 8
Notes
Dual and Quad Channel Products Only
Input-Input Insulation Leakage Current Resistance (Input-Input) Capacitance (Input-Input) II-I RI-I CI-I 0.5 1013 1.5 nA pF RH = 45%, TA = 25C, VI-I = 500 V, t = 5 s VI-I = 500 V f = 1 MH 9 9 9
Notes: 1. Peak Forward Input Current pulse width < 50 s at 1 KHz maximum repetition rate. 2. Each channel of a multichannel device. 3. Duration of output short circuit time not to exceed 10 ms. 4. All devices are considered two-terminal devices: measured between all input leads or terminals shorted together and all output leads or terminals shorted together. 5. This is a momentary withstand test, not an operating condition. 6. CML is the maximum rate of rise of the common mode voltage that can be sustained with the output voltage in the logic low state (VO < 0.8 V). CMH is the maximum rate of fall of the common mode voltage that can be sustained with the output voltage in the logic high state (VO > 2.0 V). 7. tPHL propagation delay is measured from the 50% point on the leading edge of the input pulse to the 1.3 V point on the leading edge of the output pulse. The tPLH propagation delay is measured from the 50% point on the trailing edge of the input pulse to the 1.3 V point on the trailing edge of the output pulse. 8. Measured between each input pair shorted together and all output connections for that channel shorted together. 9. Measured between adjacent input pairs shorted together for each multichannel device. 10. Zero-bias capacitance measured between the LED anode and cathode. 11. Standard parts receive 100% testing at 25C (Subgroups 1 and 9). SMD and hi-rel parts receive 100% testing at 25, 125, and -55C (Subgroups 1 and 9, 2 and 10, 3 and 11, respectively). 12. Parameters are tested as part of device initial characterization and after design and process changes. Parameters guaranteed to limits specified for all lots not specifically tested.
Figure 1. Typical Logic Low Output Voltage vs. Temperature.
Figure 2. Typical Logic High Output Current vs. Temperature.
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Figure 3. Output Voltage vs. Forward Input Current.
Figure 4. Typical Diode Input Forward Characteristic.
VCC PULSE GEN. tr = tf = 5 ns t = 100 kHz 10 % DUTY CYCLE IF INPUT MONITORING NODE OUTPUT VO MONITORING NODE VCC
VO
D.U.T.
5V D1 619
VE Rf
CL= 15 pF 5K
D2 D3 D4
GND
THE PROBE AND JIG CAPACITANCES ARE INCLUDED IN CL.
Figure 5. Test Circuit for tPLH, tPHL, tr, and tf.
Figure 6. Typical Propagation Delay vs. Temperature.
Figure 7. Typical Rise, Fall Time vs. Temperature.
1-520
PULSE GENERATOR ZO = 50 tr = tf = 5 ns
CL= 15 pF INCLUDING PROBE AND JIG CAPACITANCE. VCC D.U.T. VCC VO D1
+5 V
S1 619
D1-4 ARE 1N916 OR 1N3064
IF
VO CL
VE GND INPUT VO MONITORING NODE
D2 5 K D3 D4
S2
Figure 8. Test Circuit for tPHZ, tPZH, tPLZ, and tPZL.
A D.U.T. B RIN VCC VO
VCC OUTPUT VO MONITORING NODE
VE VFF GND
0.1 F BYPASS
VCM + - PULSE GEN.
*SEE NOTE 6.
Figure 9. Test Circuit for Common Mode Transient Immunity and Typical Waveforms.
VCC1 (+5 V) 665 D.U.T. VCC DATA INPUT VO
TTL OR LSTTL
VCC2 (4.5 TO 20 V)
RL CMOS
DATA OUTPUT
VCC1 (+5 V) 750 D.U.T. VCC DATA INPUT
TTL OR LSTTL
VE GND
TOTEM POLE OUTPUT GATE
1
VCC2 5V 10 V 15 V 20 V
RL 1.1 K 2.37 K 3.83 K 5.11 K
2
TOTEM POLE OUTPUT GATE
GND
Figure 10. LSTTL to CMOS Interface Circuit.
Figure 11. Recommended LED Drive Circuit.
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VCC1 (+5 V) 619 D.U.T. VCC 4.02 K DATA INPUT
TTL OR LSTTL
OPEN COLLECTOR GATE
GND
Figure 12. Series LED Drive with Open Collector Gate (4.02 k Resistor Shunts IOH from the LED).
VCC2 (+5 V) DATA OUTPUT VCC1 (+5 V) 665 665 D.U.T. VCC DATA INPUT
TTL OR LSTTL
UP TO 16 LSTTL LOADS OR 4 TTL LOADS 0.1 F DATA OUTPUT
TOTEM POLE OUTPUT GATE
DATA INPUT 1
TTL OR LSTTL
GND TOTEM POLE OUTPUT GATE UP TO 16 LSTTL LOADS OR 4 TTL LOADS
1
2
Figure 13. Recommended LSTTL to LSTTL Circuit.
VCC + 20 V D.U.T.* IF + - 100 VCC IO VE GND 1200
0.01 F
VIN 1.90 V
CONDITIONS: IF = 8 mA IO = -14 mA
TA = +125 C
*ALL CHANNELS TESTED SIMULTANEOUSLY.
Figure 14. Single Channel Operating Circuit for Burn-in and Steady State Life Tests.
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MIL-PRF-38534 Class H, Class K, and DESC SMD Test Program
Hewlett-Packard's Hi-Rel Optocouplers are in compliance with MIL-PRF-38534 Classes H and K. Class H devices are also in compliance with DESC drawings 5962-88768, and 5962-88769. Testing consists of 100% screening and quality conformance inspection to MIL-PRF-38534.
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